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PRELIMINARY TECHNICAL DATA
a
2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs Preliminary Technical Data AD5346/AD5347/AD5348*
FEATURES AD5346: Octal 8-Bit DAC AD5347: Octal 10-Bit DAC AD5348: Octal 12-Bit DAC Low Power Operation: 1.4 mA (max) @ 3 V Power-Down to 100 nA @ 3 V, 240 nA @ 5 V Guaranteed Monotonic by Design Over All Codes Rail-to-Rail Output Range: 0-VREF or 0-2 V REF Power-On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Readback Buffered/Unbuffered Reference Inputs 20ns WR time 38-lead TSSOP/6mm x 6mm 40-lead CSP Packaging Temperature Range: -40 C to +105 C APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Optical Networking Automatic Test Equipment Mobile Communications Programmable Attenuators Industrial Process Control GENERAL DESCRIPTION
The AD5346/AD5347/AD5348 are octal 8-, 10-, and 12bit DACs, operating from a 2.5 V to 5.5 V supply. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, and also allows a choice of buffered or unbuffered reference input. The AD5346/AD5347/AD5348 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. A readback feature allows the internal DAC registers to be read back through the digital port. The GAIN pin on these devices allows the output range to be set at 0 V to VREF or 0 V to 2 x VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on-reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. All three parts are pin-compatible, which allows the user to select the amount of resolution appropriate for their application without redesigning their circuit board.
AD5348 FUNCTIONAL BLOCK DIAGRAM
VDD AGND DGND VREFAB VREFCD
POWER-ON RESET
BUF GAIN DB11 . . . DB0
INPUT
REGISTER
DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER
STRING DAC A STRING DAC B STRING DAC C STRING DAC D
BUFFER
VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG VOUTH
INPUT
REGISTER
BUFFER
INPUT
REGISTER
BUFFER
CS RD WR A2 A1 A0
INTERFACE LOGIC
INPUT
REGISTER
BUFFER
INPUT
REGISTER
STRING DAC E
STRING DAC F STRING DAC G STRING DAC H
BUFFER
INPUT
REGISTER
BUFFER
INPUT
REGISTER
BUFFER
INPUT
REGISTER
BUFFER
CLR LDAC
POWER-DOWN LOGIC
VREFGH
VREFEF
PD
*Protected by U.S. Patent Number 5,969,657; other patents pending.
REV. PrD 08/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5346/AD5347/AD5348-SPECIFICATIONS T (V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND; C =200 pF to GND; all specifications
DD REF L L
MIN
to TMAX unless otherwise noted.)
Parameter 1 DC PERFORMANCE AD5346 Resolution Relative Accuracy Differential Nonlinearity AD5347 Resolution Relative Accuracy Differential Nonlinearity AD5348 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 Upper Deadband Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUT6 VREF Input Range VREF Input Range VREF Input Impedance
3, 4
Min
B Version Typ Max
2
Unit
Conditions/Comments
8 0.15 0.02 10 0.5 0.05 12 2 0.2 0.4 0.1 10 10 -12 -5 -60 200
1 0.25
Bits LSB LSB Bits LSB LSB Bits LSB LSB % of FSR % of FSR mV mV ppm of FSR/C ppm of FSR/C dB V
Guaranteed Monotonic By Design Over All Codes
4 0.5
Guaranteed Monotonic By Design Over All Codes
16 1 3 1 60 60
Guaranteed Monotonic By Design Over All Codes
Lower Deadband Exists Only if Offset Error Is Negative VDD = 5 V. Upper Deadband Exists Only if VREF = VDD VDD = 10% RL = 2 k to GND, 2 k to VDD; CL = 200 pF to GND; Gain = 1 Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mode and Power-Down Mode Gain = 1. Input Impedance = RDAC Gain = 2. Input Impedance = RDAC Frequency = 10 kHz Frequency = 10 kHz Rail-to-Rail Operation
1 0.25 >10 90 45 -90 -75
VDD VDD
Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 Maximum Output Voltage4, 7 DC Output Impedance Short Circuit Current Power-Up Time LOGIC INPUTS6 Input Current VIL, Input Low Voltage
V V M k k dB dB V min V max mA mA s s A V V V V pF
0.001 VDD - 0.001 0.5 25 16 2.5 5 1 0.8 0.8 0.7 1.7 3
VDD = 5 V VDD = 3 V Coming Out of Power-Down Mode. VDD = 5 V Coming Out of Power-Down Mode. VDD = 3 V
VIH, Input High Voltage Pin Capacitance LOGIC OUTPUTS6 VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V
VDD = 5 V 10% VDD = 3 V 10% VDD = 2.5 V VDD = 2.5 V to 5.5 V
0.4 VDD -1 0.4 VDD -0.5 2.5 1 0.8 5.5 1.8 1.5
V V V V V mA mA
ISINK = 2 mA ISOURCE = 2 mA ISINK = 2 mA ISOURCE = 2 mA
VIH = VDD, VIL = GND All DACs in Unbuffered Mode. In Buffered Mode, extra current is typically x A per DAC where x = 5 A + VREF/RDAC. VIH = VDD, VIL = GND
0.4 0.12
1 1
A A
-2-
REV. PrD
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
NOTES 1 See Terminology section. 2 Temperature range: B Version: -40C to +105C; typical specifications are at 25C. 3 Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = Deadband voltage/LSB size. 6 Guaranteed by design and characterisation, not production tested. 7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD and "Offset plus Gain" Error must be positive. Specifications subject to change without notice.
AC CHARACTERISTICS1
Parameter 2 Output Voltage Settling Time AD5346 AD5347 AD5348 Slew Rate Major Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
(VDD = 2.5 V to 5.5 V. RL = 2 k to GND; CL = 200 pF to GND. All specifications TMIN to TMAX unless otherwise noted.)
Min B Version3 Typ Max 6 7 8 0.7 8 0.5 1 0.5 3.5 200 -70 8 9 10 Unit s s s V/s nV-s nV-s nV-s nV-s nV-s kHz dB Conditions/Comments VREF = 2 V. See Figure 20 1/4 Scale to 3/4 Scale Change (40 H to C0 H) 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (400 H to C00 H) 1 LSB Change Around Major Carry
VREF = 2 V 0.1 V p-p. Unbuffered Mode VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz; Unbuffered Mode.
NOTES 1 Guaranteed by design and characterization, not production tested. 2 See Terminology section. 3 Temperature range: B Version: -40C to +105C; typical specifications are at 25C. Specifications subject to change without notice.
200A
IOL
TO OUTPUT PIN
CL 50pF 200A IOH
VOH (MIN)
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. PrD
-3-
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348 TIMING CHARACTERISTICS1,
Parameter Limit at TMIN, TMAX Data Write Mode (Figure 1) 0 t1 0 t2 20 t3 5 t4 4.5 t5 t6 5 5 t7 t8 4.5 5 t9 t 10 4.5 20 t 11 t 12 20 50 t 13 t 14 20 0 t 15 Data Readback Mode (Figure 2) t 16 0 t 17 0 0 t 18 t 19 20 40 0 t 20 t 21 22 35 5 t 22 30 t 23 22 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2, 3
(VDD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)
Condition/Comments CS to WR Setup Time CS to WR Hold Time WR Pulsewidth Data, GAIN, BUF Setup Time Data, GAIN, BUF Hold Time Synchronous Mode. WR Falling to LDAC Falling. Synchronous Mode. LDAC Falling to WR Rising. Synchronous Mode. WR Rising to LDAC Rising. Asynchronous Mode. LDAC Rising to WR Rising. Asynchronous Mode. WR Rising to LDAC Falling. LDAC Pulsewidth CLR Pulsewidth Time Between WR Cycles A0, A1, A2 Setup Time A0, A1, A2 Hold Time A0, A1, A2 to CS Setup Time A0, A1, A2 to CS Hold Time CS to falling edge of RD RD Pulsewidth; VDD = 3.6V to 5.5V RD Pulsewidth; VDD = 2.5V to 3.6V CS to RD Hold Time Data Access time after falling edge of RD; VDD = 3.6V to 5.5V Data Access time after falling edge of RD; VDD = 2.5V to 3.6V Bus Relinquish Time after rising edge of RD CS falling edge to Data; VDD = 3.6V to 5.5V CS falling edge to Data; VDD = 2.5V to 3.6V
Unit min min min min min min min min min min min min min min min min min min min min min max max min max max max
NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 1. Specifications subject to change without notice.
t1 CS t3 t4 DATA, GAIN, BUF t6 LDAC1 t9 LDAC2 t7
t2 t13
WR
t5
A0 - A2
t8
t16 CS
t10 t11
t17
t18 RD t21 DATA t23
t19
t20
t12 CLR A0 - A2 NOTES: 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE t14 t15
t22
Figure 2. Parallel Interface Write Timing Diagram
Figure 3. Parallel Interface Read Timing Diagram
-4-
REV. PrD
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
ABSOLUTE MAXIMUM RATINGS*
(T A = 25C unless otherwise noted)
V DD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to GND . . -0.3 V to VDD + 0.3 V Digital Output Voltage to GND . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND -0.3 V to VDD + 0.3 V V OUT to GND . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C 38-lead TSSOP Package Power Dissipation . . . . . . . . . . . (TJ max - TA)/JA mW JA Thermal Impedance . . . . . . . . . . . . . . . . . 98.3C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . 8.9C/W
40-lead CSP Package Power Dissipation . . . . . . . . . . (TJ max - TA)/JA mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 30C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . C/W Lead Temperature, Soldering (10 seconds) . . . . . . 300C IR Reflow, Peak Temperature . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5346BRU AD5346BCP AD5347BRU AD5347BCP AD5348BRU AD5348BCP
Temperature Range -40C -40C -40C -40C -40C -40C to to to to to to +105C +105C +105C +105C +105C +105C
Package Description TSSOP (Thin Shrink Small Outline Package) CSP (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) CSP (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) CSP (Chip Scale Package)
Package Option RU-38 CP-40 RU-38 CP-40 RU-38 CP-40
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5346/AD5347/AD5348 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrD
-5-
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
AD5346 PIN CONFIGURATIONS 40-lead CSP Package
VREFGH VREFAB VREFCD VREFEF
38-lead TSSOP Package
VREFGH VREFEF VREFCD VDD
30 29 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34
PD CLR GAIN WR RD CS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND DGND DGND DGND A2
GAIN
VDD
VDD
CLR
40
39
38
37 36
35 34 33 32
VOUTA 1 VOUTB 2 VOUTC 3 VOUTD 4 AGND 5 AGND 6 VOUTE 7 VOUTF 8 VOUTG 9 VOUTH 10
11 12 13 14 15 16 17 18 19 20
WR
31
PD
RD CS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VREFAB VOUTA VOUTB VOUTC VOUTD AGND VOUTE VOUTF VOUTG VOUTH DGND BUF LDAC A0 A1
8-BIT AD5346 TOP VIEW (Not to Scale)
33 32 31 30 29 28 27 26 25 24 23 22 21 20
8-BIT AD5346 TOP VIEW (Not to Scale)
27 26 25 24 23 22 21
DGND
BUF
A2
DGND
DGND
DGND
AD5346 PIN FUNCTION DESCRIPTIONS
TSSOP 1 2 3 4
Pin No. CSP 35 36 37 38,39
Mnemonic Function V REF GH V REFE F V REF CD V DD Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the CSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered Output with Rail-to-Rail Operation. Analog Ground. Ground Reference for Analog Circuitry. Digital Ground. Ground Reference for Digital Circuitry. Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. LSB Address Pin for Selecting which DAC is to Be Written to. Address Pin for Selecting which DAC is to Be Written to. MSB Address Pin for Selecting which DAC is to Be Written to. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface, or with RD to readback data from a DAC. Active Low Read Input. This is used in conjunction with CS to read data back from the internal DACS. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0- VREF or 0-2 VREF. Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode.
5 6-9, 11-14 10 15, 21-24 16 17 18 19 20 25-32 33 34 35 36 37 38
40 1-4, 7-10 5,6 11, 17-20 12 13 14 15 16 21-28 29 30 31 32 33 34
V REF AB V OUTX AGND DGND BUF LDAC A0 A1 A2 DB 0 -DB 7 CS RD WR GAIN CLR PD
DGND
A0
LDAC
A1
-6-
REV. PrD
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
AD5347 PIN CONFIGURATIONS 40-lead CSP Package
VREFGH
38-lead TSSOP Package
VREFGH VREFEF VREFCD VDD
30 29 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34
VREFAB
VREFCD
VREFEF
PD CLR GAIN WR RD CS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND DGND A2
GAIN
VDD
VDD
CLR
40
39
38
37 36
35 34 33 32
WR
31
PD
VOUTA VOUTB VOUTC VOUTD AGND AGND VOUTE VOUTF VOUTG
1 2 3 4 5 6 7 8 9
RD CS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
VREFAB VOUTA VOUTB VOUTC VOUTD AGND VOUTE VOUTF VOUTG VOUTH DGND BUF LDAC A0 A1
10-BIT AD5347 TOP VIEW (Not to Scale)
33 32 31 30 29 28 27 26 25 24 23 22 21 20
10-BIT AD5347 TOP VIEW (Not to Scale)
27 26 25 24 23 22 21
VOUTH 10
11 12 13 14 15 16 17 18 19 20
DGND
A1
DGND
DGND
LDAC
BUF
AD5347 PIN FUNCTION DESCRIPTIONS
TSSOP 1 2 3 4
Pin No. CSP 35 36 37 38,39
Mnemonic Function V REF GH V REFE F V REF CD VDD Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the CSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered Output with Rail-to-Rail Operation. Analog Ground. Ground Reference for Analog Circuitry. Digital Ground. Ground Reference for Digital Circuitry. Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. LSB Address Pin for Selecting which DAC is to Be Written to. Address Pin for Selecting which DAC is to Be Written to. Ten Parallel Data Inputs. DB9 is the MSB of these ten bits. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface, or with RD to readback data from a DAC. Active Low Read Input. This is used in conjunction with CS to read data back from the internal DACS. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0- VREF or 0-2 VREF. Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode.
5 6-9, 11-14 10 15, 21-22 16 17 18 19 23-32 33 34 35 36 37 38
40 1-4, 7-10 5,6 11, 17-18 12 13 14 15 19-28 29 30 31 32 33 34
V REF AB V OUTX AGND DGND BUF LDAC A0 A1 DB 0 -DB 9 CS RD WR GAIN CLR PD
REV. PrD
DB0
DB1
A0
A2
-7-
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
AD5348 PIN CONFIGURATIONS 40-lead CSP Package
VREFGH VREFAB VREFCD VREFEF
38-lead TSSOP Package
VREFGH VREFEF VREFCD
30 29 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34
PD CLR GAIN WR RD CS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A2
GAIN
VDD
VDD
CLR
40
39
38
37 36
35 34 33 32
PD
WR
31
VOUTA VOUTB VOUTC VOUTD AGND AGND VOUTE VOUTF VOUTG
1 2 3 4 5 6 7 8 9
RD CS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
VDD VREFAB VOUTA VOUTB VOUTC VOUTD AGND VOUTE VOUTF VOUTG VOUTH DGND BUF LDAC A0 A1
12-BIT AD5348 TOP VIEW (Not to Scale)
33 32 31 30 29 28 27 26 25 24 23 22 21 20
12-BIT AD5348 TOP VIEW (Not to Scale)
27 26 25 24 23 22 21
VOUTH 10
11 12 13 14 15 16 17 18 19 20
A1
DB1
A2
DB2
DGND
LDAC
BUF
DB0
AD5348 PIN FUNCTION DESCRIPTIONS
TSSOP 1 2 3 4
Pin No. CSP 35 36 37 38,39
Mnemonic Function V REF GH V REFE F V REF CD VDD Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the CSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered Output with Rail-to-Rail Operation. Analog Ground. Ground Reference for Analog Circuitry. Digital Ground. Ground Reference for Digital Circuitry. Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. LSB Address Pin for Selecting which DAC is to Be Written to. Address Pin for Selecting which DAC is to Be Written to. MSB Address Pin for Selecting which DAC is to Be Written to. Twelve Parallel Data Inputs. DB11 is the MSB of these twelve bits. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface, or with RD to readback data from a DAC. Active Low Read Input. This is used in conjunction with CS to read data back from the internal DACS. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0- VREF or 0-2 VREF. Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode. -8- REV. PrD
5 6-9, 11-14 10 15 16 17 18 19 20 21-32 33 34 35 36 37 38
40 1-4, 7-10 5,6 11 12 13 14 15 16 17-28 29 30 31 32 33 34
V REF AB V OUTX AGND DGND BUF LDAC A0 A1 A2 DB 0 -DB 11 CS RD WR GAIN CLR PD
DB3
A0
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
TERMINOLOGY RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL versus Code plot can be seen in TPC's 1, 2, and 3.
DIFFERENTIAL NONLINEARITY
OUTPUT VOLTAGE
GAIN ERROR AND OFFSET ERROR
ACTUAL
Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plot can be seen in TPC's 4, 5, and 6.
OFFSET ERROR
IDEAL
POSITIVE OFFSET
This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage will still be positive at zero input code. This is shown in Figure 5. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there will be a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code there will be a deadband over which the output voltage will not change. This is illustrated in Figure 6.
GAIN ERROR
DAC CODE
Figure 5. Positive Offset Error and Gain Error
IDEAL OUTPUT VOLTAGE
GAIN ERROR AND OFFSET ERROR
ACTUAL
This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illustrated in Figure 4.
NEGATIVE OFFSET
DAC CODE
DEADBAND CODES
POSITIVE GAIN ERROR ACTUAL NEGATIVE GAIN ERROR
AMPLIFIER FOOTROOM (~1mV)
OUTPUT VOLTAGE
NEGATIVE OFFSET
IDEAL
Figure 6. Negative Offset Error and Gain Error
DAC CODE
Figure 4. Gain Error
REV. PrD
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
OFFSET ERROR DRIFT DIGITAL CROSSTALK
This is a measure of the change in Offset Error with changes in temperature. It is expressed in (ppm of fullscale range)/C.
GAIN ERROR DRIFT
This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV secs.
ANALOG CROSSTALK
This is a measure of the change in Gain Error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied 10%.
DC CROSSTALK
This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV secs.
DAC-TO-DAC CROSSTALK
This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in V.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.
CHANNEL-TO-CHANNEL ISOLATION
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC pin set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs.
MULTIPLYING BANDWIDTH
This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference inputs of the other DACs. It is measured by grounding one VREF pin and applying a 10 kHz, 4 V peak-to-peak sine wave to the other VREF pins. It is expressed in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
The amplifiers within the DAC have a finite bandwidth. The Multiplying Bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The Multiplying Bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
Major-Code Transition Glitch Energy is the energy of the impulse injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.
Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to (CS held high). It is specified in nV-secs and is measured with a full-scale change on the digital input pins, i.e. from all 0s to all 1s and vice versa.
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REV. PrD
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
FUNCTIONAL DESCRIPTION
The AD5346/AD5347/AD5348 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers offer railto-rail output swing. The gain of the buffer amplifiers can be set to 1 or 2 to give an output voltage range of 0 to VREF or 0 to 2 VREF. The AD5346/AD5347/AD5348 have reference inputs that may be buffered to draw virtually no current from the reference source. The devices have a power-down feature that reduces current consumption to only 100 nA @ 3 V.
Digital-to-Analog Section
VREF R
R TO OUTPUT AMPLIFIER
R
R
R
The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 5 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by:
VOUT = VREF x D 2N x Gain
Figure 8. Resistor String
DAC Reference Input
where: D = decimal equivalent of the binary code which is loaded to the DAC register: 0-255 for AD5346 (8 Bits) 0-1023 for AD5347 (10 Bits) 0-4095 for AD5348 (12 Bits) N = DAC resolution Gain = Output Amplifier Gain (1 or 2)
VREF AB
The DACs operate with an external reference. The AD5346/AD5347/AD5348 has a reference input for each pair of DACs. The reference inputs may be configured as buffered or unbuffered. This option is controlled by the BUF pin. In buffered mode (BUF = 1) the current drawn from an external reference voltage is virtually zero, as the inpedance is at least 10 M. The reference input range is 1 V to VDD. In unbuffered mode (BUF = 0) the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 90 k for 0-VREF mode and 45 k for 0-2 VREF mode. If using an external buffered reference (e.g. REF192) there is no need to use the on-chip buffer.
Output Amplifier
BUF
REFERENCE BUFFER (Gain = 1 OR 2)
INPUT REGISTER
DAC REGISTER
RESISTOR STRING OUTPUT BUFFER AMPLIFIER
VOUTA
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on VREF, GAIN, the load on VOUT and offset error. If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 VREF. However because of clamping the maximum output is limited to VDD - 0.001 V. The output amplifier is capable of driving a load of 2 k to GND or VDD , in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in TPC 7. The slew rate is 0.7 V/s with a half-scale settling time to 0.5 LSB (at 8 bits) of 6 s with the output unloaded. See TPC 10.
Figure 7. Single DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 6. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
PARALLEL INTERFACE POWER-ON RESET
The AD5346, AD5347, and AD5348 load their data as a single 8-, 10-, or 12-bit word.
Double-Buffered Interface
The AD5346/AD5347/AD5348 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is: * Normal operation * Reference Input Buffered * 0 - VREF output range * Output voltage set to 0 V Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5346/AD5347/AD5348 DACs all have doublebuffered interfaces consisting of an input register and a DAC register. DAC data, BUF and GAIN inputs are written to the input register under control of the Chip Select (CS) and Write (WR). Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also doublebuffered and are only updated when LDAC is taken low. This is useful if the user requires simultaneous updating of all DACs and peripherals. The user may write to all input registers individually and then, by pulsing the LDAC input low, all outputs will update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5346/AD5347/AD5348, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk.
Clear Input (CLR CLR) CLR
The AD5346/AD5347/AD5348 have low power consumption, dissipating typically 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by taking pin PD low. When the PD pin is high, the DACs work normally with a typical power consumption of 1 mA at 5 V (0.8 mA at 3 V). In power-down mode, however, the supply current falls to 240 nA at 5 V (100 nA at 3 V) when the DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the outputs are three-state while the part is in powerdown mode, and provides a defined input condition for whatever is connected to the outputs of the DAC amplifiers. The output stage is illustrated in Figure 7.
CLR is an active low, asynchronous clear that resets the input and DAC registers.
Chip Select Input (CS CS) CS
CS is an active low input that selects the device.
Write Input (WR WR) WR
RESISTOR STRING DAC
AMPLIFIER
VOUT
WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR.
Read Input (RD RD) RD
POWER-DOWN CIRCUITRY
Figure 9. Output Stage During Power-Down
RD is an active low input that controls when data is readback from the internal DAC registers. Data is latched into the input register on the rising edge of RD.
Load DAC Input (LDAC LDAC) LDAC
LDAC transfers data from the input register to the DAC register (and hence updates the outputs). Use of the LDAC function enables double buffering of the DAC data, GAIN data and BUF. There are two LDAC modes: Synchronous Mode: In this mode the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed as in Figure 1. Asynchronous Mode: In this mode the outputs are not updated at the same time that the input register is written to. When LDAC goes low the DAC register is updated with the contents of the input register.
The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD = 3 V. This is the time from a rising edge on the PD pin to when the output voltage deviates from its power-down voltage. See TPC 15 .
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
Table I. AD5346/AD5347/AD5348 Truth Table
CLR 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X
LDAC 1 1 X 1 1 1 1 1 1 1 1 X X X X X X X X 0 X
CS 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X
WR X 1 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0
RD X 1 X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0
A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X
A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X
A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X
Function No Data Transfer No Data Transfer Clear All Registers Load DAC A Input Register Load DAC B Input Register Load DAC C Input Register Load DAC D Input Register Load DAC E Input Register Load DAC F Input Register Load DAC G Input Register Load DAC H Input Register Readback DAC Register A Readback DAC Register B Readback DAC Register C Readback DAC Register D Readback DAC Register E Readback DAC Register F Readback DAC Register G Readback DAC Register H Update DAC Registers Invalid Operation
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
X = don't care. .
SUGGESTED DATABUS FORMATS
In many applications the GAIN and BUF are hardwired. However, if more flexibility is required, they can be included in a data bus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system GAIN and BUF may be treated as data inputs since it is written to the device during a write operation and takes effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. The AD5347 and AD5348 databus must be at least 10, and 12 bits wide respectively, and are best suited to a 16bit databus system. Examples of data formats for putting GAIN and BUF on a 16-bit databus are shown in Figure 8. Note that any unused bits above the actual DAC data may be used for GAIN and BUF.
APPLICATIONS INFORMATION Typical Application Circuits
The AD5346/AD5347/AD5348 can be used with a wide range of reference voltages, especially if the reference inputs are configured as unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices may be used with a fixed, precision reference voltage. Figure 11 shows a typical setup for the devices when using an external reference connected to the reference inputs. Suitable references for 5 V operation are the AD780, ADR381 and REF192 (2.5 V references). For 2.5 V operation, suitable external references would be the AD589 and the AD1580 (1.2 V bandgap references).
VDD = 2.5V TO 5.5V
0.1 F VIN
10 F
AD5347
X X X X BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
EXT REF
GND
VDD VOUT VREF* VOUT*
AD5348
X X BUF GAIN DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD5346/AD5347/ AD5348
X = UNUSED BIT
Figure 10. AD5347/AD5348 Data Format for Word Load with GAIN and BUF Data on 16-Bit Bus
AD780/ADR381/REF192 WITH VDD = 5V OR AD589/AD1580 WITH VDD = 2.5V *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
GND
Figure 11. AD5346/AD5347/AD5348 Using an External Reference
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
Driving VDD from the Reference Voltage
where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. With REFIN = 5 V, R1 = R2 = 10 k: VOUT = (10 x D/2N) - 5 V
If an output range of zero to VDD is required, the simplest solution is to connect the reference inputs to VDD. As this supply may not be very accurate, and may be noisy, the devices may be powered from the reference voltage, for example using a 5 V reference such as the ADM663 or ADM666, as shown in Figure 12.
6V TO 16V
Decoding Multiple AD5346/AD5347/AD5348
0.1 F 10 F
VIN ADM663/ADM666 SENSE VOUT(2) VSET GND SHDN VDD VREF* 0.1 F VOUT*
The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only the CS to one of the DACs will be active at any one time, so data will only be written to the DAC whose CS is low.
AD5346/AD5347/ AD5348
GND
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
Figure 12. Using an ADM663/ADM666 as Power and Reference to the AD5346/AD5347/AD5348
Bipolar Operation Using the AD5346/AD5347/AD5348
The 74HC139 is used as a 2- to 4-line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 14 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to zero.
The AD5346/AD5347/AD5348 have been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 13. This circuit will give an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820, the AD8519 or an OP196 as the output amplifier.
5V R4 20k 0.1 F 10 F R3 10k VIN EXT REF GND VDD VOUT 0.1 F VREF* +5V
A0 A1 A2 WR LDAC CLR
A0 A1 A2 WR LDAC CLR CS
AD5346/AD5347/ AD5348
DATA INPUTS
5V AD820/AD8519/ OP196 - 5V R1 10k R2 20k GND
ENABLE CODED ADDRESS
1G 1A
VCC 1Y0 1Y1 74HC139 1Y2 1Y3 DGND
AD5346/AD5347/ AD5348
VOUT*
1B
A0 A1 A2 WR LDAC CLR CS
AD5346/AD5347/ AD5348
DATA INPUTS
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
Figure 13. Bipolar operation with the AD5346/AD5347/ AD5348
A0 A1 A2 WR LDAC CLR CS
AD5346/AD5347/ AD5348
DATA INPUTS
The output voltage for any input code can be calculated as follows: VOUT = [(REFIN x D/2N) x (R1 + R2)/R1 - REFIN x (R2/ R1)] -14-
Figure 14. Decoding Multiple DAC Devices
REV. PrD
DATA BUS
VDD
A0 A1 A2 WR LDAC CLR CS
AD5346/AD5347/ AD5348
DATA INPUTS
PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
AD5334/AD5335/AD5336/AD5344 as a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using two of the DACs in the AD5346/AD5347/AD5348 is shown in Figure 15. Any pair of DACs in the device may be used, but for simplicity the description will refer to DACs A and B. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04. If a signal at the VIN input is not within the programmed window, an LED will indicate the fail condition.
5V 0.1m F 10m F VIN VREF VREFAB VDD VOUTA 1kV FAIL 1kV PASS
VDD = 5V
0.1m F
10m F VSOURCE
VIN EXT REF GND VDD VOUT 0.1m F VREF* VOUT*
5V
LOAD
AD5346/AD5347/ AD5348
4.7kV GND 470V
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
AD5346/AD5347/ AD5348
VOUTB GND
1/2 CMP04
PASS/ FAIL
Figure 16. Programmable Current Source
Coarse and Fine Adjustment Using the AD5346/AD5347/ AD5348
1/6 74HC05
Figure 15. Programmable Window Detector
Programmable Current Source
Figure 16 shows the AD5346/AD5347/AD5348 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 k in series with the 470 adjustment potentiometer, which gives an adjustment of about 5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having rail-to-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows:
I = G x V REF x D (2 N x R) mA
Two of the DACs in the AD5346/AD5347/AD5348 can be paired together to form a coarse and fine adjustment function, as shown in Figure 17. As with the window comparator previously described, the description will refer to DACs A and B. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 will change the relative effect of the coarse and fine adjustments. With the resistor values shown the output amplifier has unity gain for the DAC A output, so the output range is zero to (VREF - 1 LSB). For DAC B the amplifier has a gain of 7.6 x 10-3, giving DAC B a range equal to 2 LSBs of DAC A. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a rail-to-rail output swing.
VDD = 5V
R3 51.2kV
R4 390V 5V
0.1m F
10m F
Where: G D N R in is the is the is the is the k gain of the buffer amplifier (1 or 2) digital input code DAC resolution (8, 10, or 12 bits) sum of the resistor plus adjustment potentiometer
VIN EXT REF VOUT GND 0.1m F VREFAB
VDD VOUTA R1 390V R2 51.2kV
VOUT
AD5346/AD5347/ AD5348
VOUTB
AD780/ADR381/REF192 WITH VDD = 5V GND
Figure 17. Coarse and Fine Adjustment
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5346/AD5347/ AD5348 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD5346/ AD5347/AD5348 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD5346/ AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD5346/AD5347/ AD5348. The AD5346/AD5347/AD5348 should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
Table III. Overview of AD53xx Parallel Devices
Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344 OCTALS AD5346 AD5347 AD4348
Resolution 8 10 12 12 8 10 12 12 8 10 10 12 8 10 12
DNL 0.25 0.5 1.0 1.0 0.25 0.5 1.0 1.0 0.25 0.5 0.5 1.0 0.25 0.5 1.0
VREF Pins 1 1 1 1 2 2 2 1 2 2 4 4 4 4 4
Settling Time 6 7 8 8 6 7 8 8 6 7 7 8 s s s s s s s s s s s s 3 3 3
Additional Pin Functions BUF 3 3 3 GAIN 3 3 3 3 HBEN CLR 3 3 3 3 3 3 3 3 3 3 3
Package TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP, CSP TSSOP, CSP TSSOP, CSP
Pins 20 20 24 20 20 24 28 20 24 24 28 28 38, 40 38, 40 38, 40
3
3 3
3 3 3 3 3 3
6 s 7 s 8 s
3 3 3
3 3 3
Table IV. Overview of AD53xx Serial Devices
Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328
Resolution 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12
DNL 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0
VREF Pins 0 0 0 0 0 0 2 2 2 2 2 2 1 1 1 1 1 1 4 4 4 2 2 2 2 2 2 (Vref (Vref (Vref (Vref (Vref (Vref = = = = = = VDD) VDD) VDD) VDD) VDD) VDD)
Settling Time 4 6 8 6 7 8 6 7 8 6 7 8 6 7 8 6 7 8 6 7 8 6 7 8 s s s s s s s s s s s s s s s s s s s s s s s s
Interface SPI SPI SPI 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI
Package SOT-23, SOT-23, SOT-23, SOT-23, SOT-23, SOT-23, MicroSOIC MicroSOIC MicroSOIC MicroSOIC MicroSOIC MicroSOIC
Pins 6, 6, 6, 6, 6, 6, 8 8 8 16 16 16 10 10 10 10 10 10 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8
MicroSOIC MicroSOIC MicroSOIC TSSOP TSSOP TSSOP MicroSOIC MicroSOIC MicroSOIC MicroSOIC MicroSOIC MicroSOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
6 s 7 s 8 s
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PRELIMINARY TECHNICAL DATA AD5346/AD5347/AD5348
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
38-Lead Thin Shrink Small Outline Package TSSOP (RU-38)
0.386 (9.80) 0.378 (9.60)
38 20
0.177 (4.50)
0.169 (4.30)
0.252 (6.40)
19
0.006 (0.15) 0.002 (0.05)
PIN 1
0.0433 (1.10) MAX 8o 0o 0.028 (0.70) 0.020 (0.50)
SEATING PLANE
0.020 (0.50) BSC
0.0106 (0.27) 0.0067 (0.17)
0.0079 (0.20) 0.0035 (0.090)
40-Lead Chip Scale Package CSP (CP-40)
0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 31 0.009 (0.24)
30
BSC
0.236(6.0) BSC SQ PIN 1 INDICATOR
0.010 (0.25) MIN
40 1
TOP VIEW
0.226 (5.75) BSC SQ
BOTTOM VIEW
0.167 (4.25) 0.161 (4.10) SQ 0.156 (3.95)
0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 12 MAX 0.035 (0.90) MAX 0.033 (0.85) NOM
o
21 20
10 11
0.177 (4.5) REF
0.028 (0.70) MAX 0.026 (0.65) NOM 0.002 (0.05) 0.0004 (0.01) 0.012 (0.30) 0.020 (0.50) 0.008(0.20) 0.0 (0.0) BSC 0.009 (0.23) REF 0.007 (0.18)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
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